· B.Sc. or Master degree in Electrical or related engineering field,
· 5-7 years of experience in Architecture (SW / HW partitioning), Micro-Architecture / RTL design, and for multiple FPGA clustering design and optimizations,
· Experience with 3GPP LTE / 5G Physical Layer (PHY) design and implementation, and integration with RF solutions (preferred).
· Experience in working closely with wireless or 3GPP LTE algorithm designers, and skills to review technical documentations (preferred).
· Achieved success in releasing deliverables while meeting time, cost, scope, and quality.
· Strong hands-on experience in RTL coding using VHDL, Synthesis, Simulations, and Lab testing, and ongoing support issues.
Must be a self-starter and able to drive in a fast paced, system hardware.
Strong written/verbal communication skills.